We are looking for a hands-on Senior Technical Lead, Analog/RF ASIC Design to set technical direction, mentor a team of RF/Analog designers, and ship production silicon. You will work end-to-end across specification, design, sign-off, bring-up, and characterization, and partner closely with architecture and cross-functional teams to remove blockers and deliver tape-outs. This role reports to the Director of ASIC.

Your Responsibilities

• Own RF/analog ASIC development from concept to production; drive tape-out readiness and sign-off.
• Partner with ASIC architects to define requirements, and block specifications for RF/analog subsystems.
• Design and integrate critical RF/analog blocks; verify performance at block and top level to ensure a successful tape-out.
• Set technical direction; run design reviews; supervise schematic design, simulation, and layout to ensure first-time-right outcomes.
• Plan execution: create schedules, allocate resources, manage workload, and actively mitigate technical risk.
• Maintain, improve, and document the RF/analog development lifecycle (flows, checklists, best practices).
• Coach and mentor junior and intermediate designers; develop team capability and ensure design quality.
• Participate hands-on in lab validation, debugging, and silicon characterization; root-cause issues and drive corrective actions.
• Work with production teams to optimize designs for manufacturability, testability, yield, and manufacturing efficiency.

Your Qualifications

• MS or PhD in Electrical Engineering (or equivalent depth of experience).
• 10+ years of relevant analog/RF ASIC development with significant hands-on ownership and technical leadership experience.
• Deep knowledge of analog fundamentals (amplifiers, comparators, mixers, filters, PLL, ADCs/DACs) and mixed-signal design considerations.
• Experience with Cadence Virtuoso or Synopsys analog design flows; strong simulation and verification discipline.
• Proven ability in layout collaboration, parasitic extraction, and verification (DRC/LVS) with post-layout correlation.
• Lab experience with common equipment (protocol/logic analyzers, oscilloscopes, spectrum analyzers, etc.) for debugging and validating RF/analog ICs.
• Familiarity with silicon qualification and production-ramp considerations.
• Ability to dive into critical design issues, take ownership, and drive to closure in fast development cycles.
• Strong communication and collaboration abilities; demonstrated creative and critical thinking with rigor.

Nice to have

• Wireless transceiver experience (UWB, BLE, Wi-Fi, or similar), clocking/synthesizers, low-noise references, or ultra-low-power techniques.
• Track record leading silicon bring-up across multiple tape-outs and technology nodes.
• Experience building scalable RF/analog methodology, automation, and sign-off processes.