SPARK Microsystems is seeking a hands‑on, system‑minded ASIC / SoC Architect to define the architecture and microarchitecture of next‑generation MCU‑based ASICs. Reporting to the Director, ASIC, this is a high‑impact technical leadership role with end‑to‑end ownership, spanning early requirements definition and architectural exploration through implementation support, silicon bring‑up, and post‑silicon optimization.

In this role, you will shape foundational architectural decisions across performance, power, area (PPA), programmability, scalability, and time‑to‑market, directly influencing the success of silicon products. You will own critical architecture decisions, with a core focus on MCU‑based ASIC / SoC architecture, low‑power design, and memory and interconnect definition.

You will set the technical direction for system performance, power efficiency, area, debuggability, firmware integration, and execution risk. The ideal candidate combines deep embedded architecture expertise with strong silicon instincts and is equally effective at the whiteboard, in detailed specifications, and in the lab.

Key responsibility:

Architecture and System Definition

• Translate product requirements into clear, executable architecture and microarchitecture specifications.
• Define top‑level SoC architecture, including MCU cores, memory hierarchy (SRAM / Flash), DMA, interrupt structure, clock and reset architecture, bus interconnects (AMBA AHB/APB/AXI), and peripheral subsystems (QSPI, USB, I2C, I2S, timers, etc.).
• Define system memory maps, register maps, address allocation, debug visibility, and observability hooks.
• Develop architectural models or simulations, when required, to evaluate performance and de‑risk key decisions.

PPA, Clocking, and Low‑Power Strategy

• Drive architectural trade studies to balance performance, power, area, execution risk, and schedule.
• Define clocking strategies, including clock gating, reset topology, clock‑domain crossings, and power‑domain partitioning.
• Develop low‑power architectures covering sleep states, state retention, wake‑up behavior, and system‑level energy management.
• Ensure architectural alignment with process‑node constraints, third‑party IP limitations, and implementation tool flows.

Execution and Cross‑Functional Leadership

• Evaluate, select, and integrate third‑party IP that meets system requirements and implementation goals.
• Partner closely with firmware teams to define hardware/software partitioning, boot flows, driver assumptions, and bring‑up strategy.
• Define architecture‑level test intent, key use cases, and debug requirements to support verification and post‑silicon validation.
• Lead architecture reviews and provide technical leadership across design, verification, implementation, silicon bring‑up, and lab validation.
• What Success Looks Like

A clean, scalable architecture that meets product goals and can be executed with high confidence.
Critical PPA, clocking, memory, and low‑power trade‑offs resolved early to reduce downstream risk.
A strong hardware/firmware contract that enables efficient bring‑up and reliable silicon validation.

What you must have

• MS or PhD in Electrical Engineering, Computer Engineering, or a related field (or equivalent deep industry experience).
• 10+ years of experience in MCU‑based ASIC or SoC architecture and design, with a proven record of taking silicon to production.
• Deep expertise in Arm Cortex‑M architectures, AMBA protocols (AHB, APB, AXI), memory subsystems, interrupts, DMA, and embedded peripheral integration.
• Strong microarchitecture experience, including datapath definition, pipeline and control design, clock gating, power gating, and low‑power techniques.
• Demonstrated ability to drive architectural trade‑offs from first principles while balancing ambition with execution reality.
• Hands‑on familiarity with Synopsys digital design flows.
• Excellent communication, documentation, and cross‑functional leadership skills.
• Experience with advanced process nodes (e.g., 22nm) is highly valued.

Preferred Qualifications

Experience with on‑chip power management (LDOs, DC/DC converters, or system‑level power architecture).
Experience supporting silicon bring‑up, lab debug, and post‑silicon optimization alongside validation teams.

Why Join SPARK Microsystems

Architect real silicon with meaningful end‑to‑end ownership and visible product impact.
Work closely across architecture, firmware, design, verification, and validation.
Solve challenging embedded and low‑power system problems in a focused team where your decisions materially shape the product.